Finite-field, or Galois-field, arithmetic has the property that the result of any operation on two values within a particular finite field also falls within the field. It should be apparent that for many operations on values a finite field, that property would be easy to achieve, but for other operations, that property could become difficult to achieve. As a trivial illustration, for example, if the operation is addition, ordinary addition of values in the lower ranges of the finite field would provide a result that is still within the field, but if one of the values being operated on is the highest value in the field, then there is no ordinary addition operation that would provide a result that is still within the field (assuming all values in the field are positive).
Therefore, as is well-known, Galois-field operations, particularly when implemented in circuitry, include two stages—an expansion stage, which may result in a value outside the field, and a reduction stage, which brings that value back into the field. Building a circuit to perform Galois-field reduction is straightforward when the sizes of the field and of the operation are known. However, there are situations, particularly when designing Galois-field operations circuitry for a programmable integrated circuit device—e.g., a field-programmable gate array (FPGA), that the sizes of the field and of the operation are unknown and arbitrary, as they depend on future user needs.